PRELIMINARY
CYW43438
Table 3. Crystal Oscillator and External Clock Requirements and Performance
External Frequency Ref-
erence
Crystal
Min. Typ.
Parameter
Frequency
Conditions/Notes
Max.
–
Min. Typ.
Max.
Units
MHz
pF
–
–
–
–
–
–
37.41
–
–
–
–
–
–
–
–
–
Crystal load capacitance
ESR
12
–
–
60
Ω
External crystal must be able to
tolerate this drive level.
Drive level
200
–
–
–
–
–
μW
Resistive
–
–
–
–
–
–
–
–
–
10k 100k
–
7
Ω
pF
Input Impedance (WLRF_X-
TAL_XOP)
Capacitive
–
–
–
WLRF_XTAL_XOP input voltage AC-coupled analog signal
4002
1260
mVp-p
WLRF_XTAL_XOP input low
DC-coupled digital signal
level
–
–
–
–
–
–
–
0
–
–
–
0.2
1.26
20
V
V
WLRF_XTAL_XOP input high
DC-coupled digital signal
level
1.0
–20
Frequency tolerance
Initial + over temperature
–
–20
20
ppm
Duty cycle
37.4 MHz clock
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
–
50
–
60
%
Phase Noise3, 4, 5
(IEEE 802.11 b/g)
37.4 MHz clock at 10 kHz offset
37.4 MHz clock at 100 kHz offset
37.4 MHz clock at 10 kHz offset
37.4 MHz clock at 100 kHz offset
37.4 MHz clock at 10 kHz offset
37.4 MHz clock at 100 kHz offset
–129
–136
–134
–141
–140
–147
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–
–
Phase Noise3, 4, 5
(IEEE 802.11n, 2.4 GHz)
–
–
–
–
Phase Noise3, 4, 5
(256-QAM)
–
–
–
–
1. The frequency step size is approximately 80 Hz. The CYW43438 does not auto-detect the reference clock frequency; the frequency is
specified in the software and/or NVRAM file.
2. To use 256-QAM, a 800 mV minimum voltage is required.
3. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in
MHz.
4. Phase noise is assumed flat above 100 kHz.
5. The CYW43438 supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.
Document Number: 002-14796 Rev. *K
Page 14 of 101
CYPRESS [ CYPRESS ]
