PRELIMINARY
CYW43438
2.3 WLAN Power Management
The CYW43438 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize
power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43438 integrated RAM is a high
volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW43438 includes an advanced
WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43438 into various power management states
appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and
other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable
them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/
turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever
possible.
The CYW43438 WLAN power states are described as follows:
■
Active mode— All WLAN blocks in the CYW43438 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required
regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
■
Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43438 remains powered up in an IDLE state. All
main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This
condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leak-
age current.
■
■
Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved
and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the
digital core are restored to their pre-deep-sleep settings when a wake-up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the
PMU timers.
Power-down mode—The CYW43438 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-
enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and
a table that describes the relationship between resources and the time required to enable and disable them.
Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by
any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks.
Each resource is in one of the following four states:
■
■
■
■
enabled
disabled
transition_on
transition_off
Document No. Document Number: 002-14796 Rev. *K
Page 11 of 108
CYPRESS [ CYPRESS ]
