PRELIMINARY
CYW43438
4. WLAN System Interfaces
4.1 SDIO v2.0
The CYW43438 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high speed
4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal
notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within
the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 18 for details.
Three functions are supported:
■ Function 0 standard SDIO function. The maximum block size is 32 bytes.
■ Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.
■ Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.
4.1.1 SDIO Pin Descriptions
Table 5. SDIO Pin Descriptions
SD 4-Bit Mode
Data line 0
SD 1-Bit Mode
Data line
gSPI Mode
Data output
DATA0
DATA1
DATA2
DATA3
CLK
DATA
IRQ
NC
DO
IRQ
NC
CS
Data line 1 or Interrupt
Data line 2
Interrupt
Interrupt
Not used
Not used
Clock
Not used
Card select
Data line 3
NC
Clock
CLK
CMD
SCLK Clock
DI Data input
CMD
Command line
Command line
Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
CMD
CYW43438
SD Host
DAT[3:0]
Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)
CLK
CMD
CYW43438
SD Host
DATA
IRQ
Document Number: 002-14796 Rev. *K
Page 16 of 101
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