CYW43362
Single-Chip IEEE 802.11™
b/g/n MAC/Baseband/Radio + SDIO
The Cypress CYW43362 single-chip device provides the highest level of integration for mobile and handheld wireless systems, fea-
turing integrated IEEE 802.11™ b/g and handheld device class IEEE 802.11n. It includes a 2.4 GHz WLAN CMOS power amplifier
(PA) that meets the output power requirements of most handheld systems. An optional external low-noise amplifier (LNA) and exter-
nal PA are also supported.
Along with the integrated power amplifier, the CYW43362 also includes integrated transmit and receive baluns, further reducing the
overall solution cost.
Host interface options include SDIO v2.0 that can operate in 4b or 1b modes, and a generic gSPI mode.
Utilizing advanced design techniques and process technology to reduce active and idle power, the CYW43362 is designed to
address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power manage-
ment unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery
while maximizing battery life.
Features
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Single-band 2.4 GHz IEEE 802.11 b/g/n
■
Security:
■
Integrated WLAN CMOS power amplifier with internal
power detector and closed-loop power control
❐
Hardware WAPI acceleration engine
❐
AES and TKIP in hardware for faster data encryp-
tion and IEEE 802.11i compatibility
■
■
Internal fractional-N PLL enables the use of a wide
range of reference clock frequencies
❐
WPA™- and WPA2™- (Personal) support for pow-
erful encryption and authentication
Supports IEEE 802.15.2 external 3-wire and 4-wire
coexistence schemes to optimize bandwidth utilization
with other co-located wireless technologies such as
Bluetooth, Zigbee, or BT Smart. Also supports sECI
coexistence interface.
■
69-bump WLBGA
(4.52 mm x 2.92 mm, 0.4 mm pitch)
Programmable dynamic power management
■
■
Supports battery voltage range from 2.3V to 4.8V sup-
plies with internal switching regulator
■
■
Supports standard interfaces SDIO v2.0 (50 MHz, 4-bit
and 1-bit) and generic SPI (up to 50 MHz)
■
■
1 kbit One-Time Programmable (OTP) memory for
storing board parameters
Integrated ARM Cortex™-M3 CPU with on-chip mem-
ory enables running IEEE 802.11 firmware that can be
field-upgraded with future features.
69-bump WLBGA
(4.52 mm x 2.92 mm, 0.4 mm pitch)
■
Supports WMM®, WMM-PS, and Wi-Fi Voice Per-
sonal (upgradable to Voice Enterprise in the future)
Figure 1. CYW43362 System Block Diagram
VIO Vbatt
2.4 GHz WLAN Tx
2.4 GHz WLAN Rx
WL_RST_N
SDIO/SPI
T/R
Switch
CBF
WLAN Host I/F
CYW43362
System Clock
Sleep Clock
Coexistence Interface
Cypress Semiconductor Corporation
Document No. 002-14779 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 30, 2016
CYPRESS [ CYPRESS ]
