PRELIMINARY
CYW43340
Figure 3. Typical Power Topology
VIO 1.8–3.3V
VDDIO (sdio/spi, uart, coex,
gpio, jtag, bt-pcm, bt-uart
Shaded areas are internal to the CYW43340.
LDO2P5
Max. 70 mA
2.5V
BT Class 1 PA
VBAT
2.9–4.8V
VDDIO_RF for RF Switches
OTP (3.3V)
LDO3P3
Max. 450 mA
3.3V
iPA, iPAD
Internal
LNLDO
WL RF – AFE
Internal
LNLDO
WL RF – TX
Core Buck
Regulator
Max. 372 mA
1.35V
Internal
LNLDO
WL RF – VCO, LOGEN
WL RF – LNA
WLBGA conĮ
shown.
to Power Supply
Noise
WL_REG_ON
BT_REG_ON
Internal
LNLDO
WL RF – Rx, Rcal
FM LNA, Mixer
XO
WL RF – Synth/RF PLL
WL RF – BG
1.2V
LNLDO
Max 100 mA
BT RF
Internal
LNLDO
HSIC-DVDD/SDIO
VIO 1.8–3.3V
1.2V
Internal
LPLDO1
Internal
LNLDO
HSIC-AVDD (DFLL)
WL OTP (1.2V)
Loads Not
to Power
Supply Noise
WL BB PLL
WL Digital and Mem
BT Digital and Mem
CLDO
1.2V
Max 150 mA
Internal
LPLDO2
Always On/State Ret. Island
CLPO/Ext. LPO Buīer
Document Number: 002-14943 Rev. *L
Page 8 of 96
CYPRESS [ CYPRESS ]
