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BCM43340HKUBG 参数 Datasheet PDF下载

BCM43340HKUBG图片预览
型号: BCM43340HKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n MAC/Baseband/Radio with Integrated Bluetooth 4.0]
分类和应用:
文件页数/大小: 96 页 / 1349 K
品牌: CYPRESS [ CYPRESS ]
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PRELIMINARY  
CYW43340  
2.4 Power-Off Shutdown  
The CYW43340 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices  
in the system, remain operational. When the CYW43340 is not needed in the system, VDDIO_RF and VDDC are shut down while  
VDDIO remains powered. This allows the CYW43340 to be effectively off while keeping the I/O pins powered so that they do not draw  
extra current from any other devices connected to the I/O.  
During a low-power shut-down state, provided VDDIO remains applied to the CYW43340, all outputs are tristated, and most inputs  
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths  
or create loading on any digital signals in the system, and enables the CYW43340 to be fully integrated in an embedded device and  
take full advantage of the lowest power-savings modes.  
Two signals on the CYW43340, the frequency reference input (WRF_XTAL_CAB_OP) and the LPO_IN input, are designed to be high-  
impedance inputs that do not load down the driving signal even if the chip does not have VDDIO power applied to it.  
When the CYW43340 is powered on from this state, it is the same as a normal power-up and the device does not retain any information  
about its state from before it was powered down.  
2.5 Power-Up/Power-Down/Reset Circuits  
The CYW43340 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal  
regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required  
power-up sequences, see Section 19.: “Power-Up Sequence and Timing,” on page 87.  
Table 2. Power-Up/Power-Down/Reset Control Signals  
Signal  
Description  
WL_REG_ON  
This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the  
BT_REG_ON input to control the internal CYW43340 regulators. When this pin is high, the regulators are enabled  
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and  
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 kpull-down resistor that  
is enabled by default. It can be disabled through programming.  
BT_REG_ON  
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal  
CYW43340 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has  
an internal 200 kpull-down resistor that is enabled by default. It can be disabled through programming.  
Document Number: 002-14943 Rev. *L  
Page 10 of 96  
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