PRELIMINARY
CYW43340
6. Microprocessor and Memory Unit for Bluetooth
The Bluetooth microprocessor core is based on the ARM® Cortex™-M3 32-bit RISC processor with embedded ICE-RT debug and
JTAG interface units. It runs software from the link control (LC) layer, up to the host controller interface (HCI).
The ARM core is paired with a memory unit that contains 652 KB of ROM memory for program storage and boot ROM, 195 KB of
RAM for data scratchpad and patch RAM code. The internal ROM allows for flexibility during power-on reset to enable the same device
to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features additions. These patches
may be downloaded from the host to the CYW43340 through the UART transports. The mechanism for downloading via UART is
identical to the proven interface of the CYW4329 and CYW4330 devices.
6.1 RAM, ROM, and Patch Memory
The CYW43340 Bluetooth core has 195 KB of internal RAM which is mapped between general purpose scratch pad memory and
patch memory and 652 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory
capability enables the addition of code changes for purposes of feature additions and bug fixes to the ROM memory.
6.2 Reset
The CYW43340 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset
(POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the POR circuit is held in reset.
Document Number: 002-14943 Rev. *L
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