PRELIMINARY
CYW43340
Long Frame Sync, Master Mode
Figure 12. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
PCM_OUT
8
HIGH IMPEDANCE
7
Bit 0
Bit 0
Bit 1
Bit 1
5
6
PCM_IN
Table 8. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No. Characteristics Minimum
Typical
Maximum
Unit
MHz
1
2
3
4
5
6
7
8
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
–
–
–
–
–
–
–
–
–
12
–
41
41
0
ns
ns
ns
ns
ns
ns
ns
–
25
25
–
0
8
PCM_IN hold
8
–
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
0
25
Document Number: 002-14943 Rev. *L
Page 26 of 96
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