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BCM4330FKUBG 参数 Datasheet PDF下载

BCM4330FKUBG图片预览
型号: BCM4330FKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PBGA133, WLBGA-133]
分类和应用:
文件页数/大小: 168 页 / 1861 K
品牌: CYPRESS [ CYPRESS ]
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BCM4330 Preliminary Data Sheet  
MAC Features  
PSM  
The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control  
to the hardware, to implement the 802.11 specification. It is a microcontroller that is highly optimized for flow  
control operations, which are predominant in implementations of communication protocols. The instruction  
set and fundamental operations are simple and general, which allows algorithms to be optimized until very late  
in the design process. It also allows for changes to the algorithms to track evolving 802.11 specifications.  
The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for  
instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the  
SHM bus). The PSM also uses a scratchpad memory (similar to a register bank) to store frequently accessed and  
temporary variables.  
The PSM exercises fine-grained control over the hardware engines, by programming internal hardware  
registers (IHR). These IHRs are co-located with the hardware functions they control, and are accessed by the  
PSM via the IHR bus.  
The PSM fetches instructions from the microcode memory using an address determined by the program  
counter, instruction literal, or a program stack. For ALU operations the operands are obtained from shared  
memory, scratchpad, IHRs, or instruction literals, and the results are written into the shared memory,  
scratchpad, or IHRs.  
There are two basic branch instructions: conditional branches and ALU based branches. To better support the  
many decision points in the 802.11 algorithms, branches can depend on either a readily available signals from  
the hardware modules (branch condition signals are available to the PSM without polling the IHRs), or on the  
results of ALU operations.  
WEP  
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the  
encryption and decryption, and MIC computation and verification. The accelerators implement the following  
cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP.  
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm  
to be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with  
the TXE to encrypt and compute the MIC on transmit frames, and the RXE to decrypt and verify the MIC on  
receive frames.  
®
BROADCOM  
BCM4330 Preliminary Data Sheet  
April 28, 2011 • 4330-DS304-RI  
Page 87  
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