BCM4330 Preliminary Data Sheet
Generic SPI Mode
Figure 32 shows the WLAN boot-up sequence from power-up to firmware download.
VDDIO
WL_REG_ON
< 1.5 ms
VDDC
(from internal PMU)
< 104 ms
Internal POR
After a fixed delay following Internal POR and WL_RST_N going high,
the device responds to host F0 (address 0x14) reads.
< 4 ms
Device requests for reference clock
8 ms
After 8 ms the reference clock is
assumed to be up. Access to PLL
registers is possible.
Host Interaction:
Host polls F0 (address 0x14) until it reads a
predefined pattern.
Host sets wake-up-wlan bit and
waits 8 ms, the maximum time for
reference clock availability.
After 8 ms, host programs PLL
registers to set crystal frequency
Chip active interrupt is asserted after the PLL locks
Host downloads
code.
Figure 32: WLAN Boot-Up Sequence
®
BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 83
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