BCM4330 Preliminary Data Sheet
Generic SPI Mode
Table 16: gSPI Registers (Cont.)
Bit Access Default Description
Address Register
x0002
Status enable
0
1
2
R/W
R/W
R/W
1
0
0
0: no status sent to host after read/write
1: status sent to host after read/write
0: do not interrupt if status is sent
1: interrupt host even if status is sent
0: response delay applicable to F1 read only
Interrupt with status
Response delay for all
1: response delay applicable to all function
read
x0003
x0004
Reserved
Interrupt register
–
0
–
R/W
–
0
–
Requested data not available; Cleared by
writing a 1 to this location
1
2
5
6
7
5
6
7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
F2/F3 FIFO underflow due to last read
F2/F3 FIFO overflow due to last write
F2 packet available
F3 packet available
F1 overflow due to last write
F1 Interrupt
x0005
Interrupt register
F2 Interrupt
F3 Interrupt
x0006– Interrupt enable register 15:0 R/W/U 16'hE0E7 Particular Interrupt is enabled if a
x0007
corresponding bit is set
x0008– Status register
x000B
31:0
R
32'h0000 Same as status bit definitions
x000C– F1 info register
x000D
0
1
R
R
1
0
F1 enabled
F1 ready for data transfer
F1 max packet size
F2 enabled
13:2 R/U
0
1
12'h40
1
0
x000E– F2 info register
x000F
R/U
R
F2 ready for data transfer
15:2 R/U
14'h800 F2 max packet size
x0010– F3 info register
x0011
0
1
R/U
R
1
0
F3 enabled
F3 ready for data transfer
15:2 R/U
14'h800 F3 max packet size
x0014– Test–Read only register 31:0
x0017
R
32'hFEED This register contains a predefined pattern,
BEAD
which the host can read and determine if the
gSPI interface is working properly.
x0018– Test–R/W register
x001B
31:0 R/W/U 32'h0000 This is a dummy register where the host can
0000
write some pattern and read it back to
determine if the gSPI interface is working
properly.
®
BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 82
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