PRELIMINARY
CYW20713
7.2 Ball Maps
Figure 8 shows the top view of the 50-ball 4.5 x 4 x 0.6 mm (FPBGA).
Figure 8. 50-Ball 4.5 x 4 x 0.6 mm (FPBGA) Array
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
Table 9. Ball Map for the 50-Ball CYW20713A1KUFBXG
1
2
VREGHV
REG_EN
VSS
3
4
LPO_IN
RST_N
TM0
5
6
7
VSS
8
A
B
C
D
E
F
VREG
VDDIF
VDDTF
RFP
VBAT
GPIO_1
–
VDDC
VDDO
COEX_IN
VSS
SPIM_CLK
VDDC
GPIO_0
GPIO_7
SPIM_CS_N
UART_RTS_N
SDA
–
–
UART_TXD
UART_RXD
UART_CTS_N
VDDC
VSS
VSS
–
–
VDDLNA
VDDRF
VDDPX
–
GPIO6
TM2
COEX_OUT0
PCM_CLK
RES
COEX_OUT1
PCM_SYNC
VDDO
GPIO_5
PCM_IN
PCM_OUT
VSS
SCL
G
XIN
XOUT
VSS
VDDO
Document Number: 002-14806 Rev. *C
Page 27 of 52
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