PRELIMINARY
CYW20713
7. Pin Information
7.1 Pin Descriptions
Table 8. CYW20713 Signal Descriptions
FPBGA
WLBGA
42-Bump
Power Do-
Signal
50-Ball
I/O
Description
main
Radio
RES
External calibration resistor,
15 kΩ @ 1%
G4
D6
O
VDD_RF
RFP
RF I/O antenna port
Crystal or reference input
Crystal oscillator output
D1
G2
G3
C7
F5
E5
I/O
I
VDD_RF
VDD_RF
VDD_RF
XIN
XOUT
O
Analog
LPO_IN
Voltage Regulators
REG_EN
VBAT
External LPO input
A4
B4
I
VDDRF
HV LDO and main enable
HV LDO input
B2
A3
A2
A1
B5
A5
A6
A7
I
I
VDDO
N/A
VREGHV
VREG
HV LDO output: main LDO input
Main LDO output
I/O
O
N/A
N/A
Straps
RST_N
TM0
Active-low reset input
B4
C4
–
C5
–
I
I
I
I
VDDO
VDDO
VDDO
VDDO
Clock request polarity select
Internally connected to ground
Reserved: connect to ground.
TM1
–
TM2
F3
C6
Digital I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO/BT_WAKE
GPIO/HOST_WAKE
GPIO
B5
B3
–
C3
B3
–
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
GPIO/LINK_IND
–
–
Note: Can be configured for active high or low as
well as open drain.
GPIO_4
GPIO_5
GPIO
–
–
I/O
I/O
VDDO
VDDO
GPIO/CLK_REQ
E6
F4
TCXO-OR Function Out available on some
packages.SeeSection10.:“OrderingInformation,”
on page 50.
GPIO_6
GPIO
E3
D5
I/O
VDDO
TCXO-OR Function In available on some
packages.SeeSection10.:“OrderingInformation,”
on page 50.
GPIO_7
DETATCH/CARD_DETECT
UART receive data
B7
D8
C8
D7
E8
–
I/O
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
VDDO
UART_RXD
UART_TXD
UART_RTS_N
UART_CTS_N
D2
C2
F2
E3
UART transmit data
UART request to send output
UART clear to send input
Document Number: 002-14806 Rev. *C
Page 25 of 52
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