PRELIMINARY
CYW20710
5. Peripheral Transport Unit
This section discusses the PCM, UART, and SPI peripheral interfaces. The CYW20710 has a 1040 byte transmit and receive fifo,
which is large enough to hold the entire payload of the largest EDR BT packet (3-DH5).
5.1 PCM Interface
The CYW20710 PCM interface can connect to linear PCM codec devices in master or slave mode. In master mode, the device
generates the PCM_BCLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM
interface as inputs to the device.
The device supports up to three SCO or eSCO channels through the PCM interface and each channel can be independently mapped
to any available slot in a frame.
The host can adjust the PCM interface configuration using vendor-specific HCI commands or it can be setup in the configuration file.
5.1.1 System Diagram
Figure 5 shows options for connecting the device to a PCM codec device as a master or a slave.
Figure 5. PCM Interface with Linear PCM Codec
PCM_IN
PCM_OUT
PCM_BCLK
PCM_SYNC
PCM Codec
(Master)
CYW20710
(Slave)
PCM Interface Slave Mode
PCM_IN
PCM_OUT
PCM_BCLK
PCM_SYNC
PCM Codec
(Slave)
CYW20710
(Master)
PCM Interface Master Mode
PCM_IN
PCM_OUT
PCM_BCLK
PCM_SYNC
PCM Codec
(Hybrid)
CYW20710
(Hybrid)
PCM Interface Hybrid Mode
5.1.2 Slot Mapping
The device supports up to three simultaneous, full-duplex SCO or eSCO channels. These channels are time-multiplexed onto the
PCM interface using a time slotting scheme based on the audio sampling rate, as described in Table 3.
Document No. 002-14804 Rev. *H
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CYPRESS [ CYPRESS ]
