PRELIMINARY
CYW20710
4. Microprocessor Unit
The CYW20710 microprocessor unit runs software from the Link Control (LC) layer up to the Host Controller Interface (HCI). The
microprocessor is based on the ARM7TDMIS 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The
microprocessor also includes 384 KB of ROM memory for program storage and boot ROM, 112 KB of RAM for data scratch-pad, and
patch RAM code.
The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations,
including automatic host transport selection from SPI or UART, with or without external NVRAM. At power-up, the lower layer protocol
stack is executed from the internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches
can be downloaded from the host to the device through the SPI or UART transports, or using external NVRAM. The device can also
support the integration of user applications and profiles using an external serial flash memory.
4.1 NVRAM Configuration Data and Storage
4.1.1 Serial Interface
The CYW20710 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic. Data is transferred to and from the module by the system
CPU. DMA operation is not supported.
The CYW20710 supports serial flash vendors Atmel, MXIC, and Numonyx. The most commonly used parts from two of these vendors
are:
■
■
AT25BCM512B, manufactured by Atmel
MX25V512ZUI-20G, manufactured by MXIC
4.2 EEPROM
The CYW20710 includes a Broadcom® Serial Control (BSC) master interface. The BSC interface supports low-speed and fast mode
devices and is compatible with I2C slave devices. Multiple I2C master devices and flexible wait state insertion by the master interface
or slave devices are not supported. The CYW20710 provides 400 kHz, full speed clock support.
The BSC interface is programmed by the CPU to generate the following BSC transfer types on the bus:
■
■
■
■
Read-only
Write-only
Combined read/write
Combined write-read
NVRAM may contain configuration information about the customer application, including the following:
■
■
■
■
■
Fractional-N information
BD_ADDR
UART baud rate
SDP service record
File system information used for code, code patches, or data
4.3 External Reset
The CYW20710 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action
can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset state.
The RST_N signal input is an active-low signal for all versions of the CYW20710. The CYW20710 requires an external pull-up resistor
on the RST_N input. Alternatively, the RST_N input can be connected to REG_EN or driven directly by a host GPIO.
Document No. 002-14804 Rev. *H
Page 15 of 50
CYPRESS [ CYPRESS ]
