I2C Control and Status
I2CS
7FA5
b7
b6
b5
b4
b3
b2
b1
b0
DONE
START
STOP
LASTRD
ID1
ID0
BERR
ACK
I2C Data
I2DAT
7FA6
b7
b6
b5
b4
b3
b2
b1
b0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-7. FC Registers
The 8051 uses the two registers shown in Figure 4-7 to conduct I2C transfers. The 8051
transfers data to and from the I2C bus by writing and reading the I2DAT register. The
12CS register controls I2C transfers and reports various status conditions. The three con-
trol bits are START, STOP, and LASTRD. The remaining bits are status bits. Writing to a
status bit has no effect.
4.6
Control Bits
4.6.1 START
The 8051 sets the START bit to 1 to prepare an I2C bus transfer. If START=1, the next
8051 load to I2DAT will generate the start condition followed by the serialized byte of
data in I2DAT. The 8051 loads data in the format shown in Figure 4-5 after setting the
START bit. The I2C controller clears the START bit during the ACK interval (clock 9 in
Figure 4-5).
4.6.2 STOP
The 8051 sets STOP=1 to terminate an I2C bus transfer. The I2C controller clears the
STOP bit after completing the STOP condition. If the 8051 sets the STOP bit during a
byte transfer, the STOP condition will be generated immediately following the ACK phase
of the byte transfer. If no byte transfer is occurring when the STOP bit is set, the STOP
condition will be carried out immediately on the bus. Data should not be written to I2CS
Page 4-8
Chapter 4. EZ-USB CPU
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
