2
2
Multiple I C Bus Masters — The EZ-USB chip acts only as an I C bus master,
never a slave. However, the 8051 can detect a second master by checking for
BERR=1 (Section 4.7, "Status Bits").
start
SA3
1
SA2
2
SA1
3
SA0
4
DA2
5
DA1
6
DA0
7
R/W
8
ACK
9
D7
10
D6
11
SDA
SCL
2
Figure 4-6. Addressing an I C Peripheral
The first byte of an I2C bus transaction contains the address of the desired peripheral.
Figure 4-7 shows the format for this first byte, which is sometimes called a control byte.
A master sends the bit sequence shown in Figure 4-6 after sending a START condition.
The master uses this 9-bit sequence to select an I2C peripheral at a particular address, to
establish the transfer direction (using R/W#), and to determine if the peripheral is present
by testing for ACK#.
The four most significant bits SA3-SA0 are the peripheral chip’s slave address. I2C
devices are pre-assigned slave addresses by device type, for example slave address 1010 is
assigned to EEPROMS. The three bits DA2-DA0 usually reflect the states of I2C device
address pins. Devices with three address pins can be strapped to allow eight distinct
addresses for the same device type. The eighth bit (R/W#) sets the direction for the ensu-
ing data transfer, 1 for master read, and 0 for master write. Most address transfers are fol-
lowed by one or more data transfers, with the STOP condition generated after the last data
byte is transferred.
In Figure 4-6, a READ transfer follows the address byte (at clock 8, the master sets the R/
W# bit high, indicating READ). At clock 9, the peripheral device responds to its address
by asserting ACK. At clock 10, the master floats SDA and issues SCL pulses to clock in
SDA data supplied by this slave.
Assuming the 12-MHz crystal used by the EZ-USB family, the SCL frequency is 90.9
KHz, giving an I2C transfer rate of 11 ms per bit.
EZ-USB TRM v1.9
Chapter 4. EZ-USB CPU
Page 4-7
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