Table C-17. EIP Register - SFR F8h
Bit
Function
EIP.7-5
EIP.4
Reserved. Read as 1.
PX6 - External interrupt 6 priority control. PX6 = 0 sets
external interrupt 6 (INT6) to low priority. PX6 = 1 sets
external interrupt 6 to high priority.
EIP.3
EIP.2
EIP.1
PX5 - External interrupt 5 priority control. PX5 = 0 sets
external interrupt 5 (INT5#) to low priority. PX5=1 sets
external interrupt 5 to high priority.
PX4 - External interrupt 4 priority control. PX4 = 0 sets
external interrupt 4 (INT4) to low priority. PX4=1 sets
external interrupt 4 to high priority.
PI2C - External interrupt 3 priority control. PI2C = 0 sets I2C
interrupt to low priority. PI2C=1 sets I2C interrupt to high
priority.
EIP.0
PUSB - External interrupt 2 priority control. PUSB = 0 sets
USB interrupt to low priority. PUSB=1 sets USB interrupt to
high priority.
C.4
Interrupt Processing
When an enabled interrupt occurs, the 8051 core vectors to the address of the interrupt service
routine (ISR) associated with that interrupt, as listed in Table C-18.. The 8051 core executes
the ISR to completion unless another interrupt of higher priority occurs. Each ISR ends with a
RETI(return from interrupt) instruction. After executing the RETI, the CPU returns to the
next instruction that would have been executed if the interrupt had not occurred.
An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-level
interrupt can only be interrupted by high-level interrupt. An ISR for a high-level interrupt can
only be interrupted by the resume interrupt.
The 8051 core always completes the instruction in progress before servicing an interrupt. If
the instruction in progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs,
the 8051 core completes one additional instruction before servicing the interrupt.
C.4.1 Interrupt Masking
The EA bit in the IE SFR (IE.7) is a global enable for all interrupts except the USB wakeup
(resume) interrupt. When EA = 1, each interrupt is enabled or masked by its individual enable
bit. When EA = 0, all interrupts are masked, except the USB wakeup interrupt.
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 33
CYPRESS [ CYPRESS ]
