12.14 Global USB Registers
SUDPTRH
Setup Data Pointer High
7FD4
b7
b6
b5
b4
b3
b2
b1
b0
A15
A14
A13
A12
A11
A10
A9
A8
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
SUDPTRL
Setup Data Pointer Low
7FD5
b7
b6
b5
b4
b3
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Figure 12-30. Setup Data Pointer High/Low Registers
When the EZ-USB chip receives a “Get_Descriptor” request on endpoint zero, it can
instruct the EZ-USB core to handle the multi-packet IN transfer by loading these registers
with the address of an internal table containing the descriptor data. The descriptor data
tables may be placed in internal program/data RAM or in unused Endpoint 0-7 RAM. The
SUDPTR does not operate with external memory. The SUDPTR registers should be
loaded in HIGH/LOW order.
In addition to loading SUDPTRL, the 8051 must also clear the HSNAK bit in the EP0CS
register (by writing a “1” to it) to complete the CONTROL transfer.
Note
Any host request that uses the EZ-USB Setup Data Pointer to transfer IN data must indi-
cate the number of bytes to transfer in bytes 6 (wLenghthL) and 7 (wLengthH) of the
SETUP packet. These bytes are pre-assigned in the USB Specification to be length bytes
in all standard device requests such as “Get_Descriptor.” If vendor-specific requests are
used to transfer large blocks of data using the Setup Data Pointer, they must include this
pre-defined length field in bytes 6-7 to tell the EZ-USB core how many bytes to transfer
using the Setup Data Pointer.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-37
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