OUTnCS
Endpoint (1-7) OUT Control and Status
7FC6-7FD2*
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
-
-
OUTnBSY OUTnSTL
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
* See Table 12-5 for individual control/status register addresses.
Figure 12-28. OUT Control and Status Registers
Bit 1:
OUTnBSY OUT Endpoint (1-7) Busy
The BSY bit indicates the status of the endpoint’s OUT Buffer OUTnBUF. The EZ-USB
core sets BSY=0 when the host data is available in the OUT buffer. The 8051 sets BSY=1
by loading the endpoint’s byte count register.
When BSY=1, endpoint RAM data is invalid--the endpoint buffer has been emptied by the
8051 and is waiting for new OUT data from the host, or it is the process of being loaded
over the USB. BSY=0 when the USB OUT transfer is complete and endpoint RAM data
in OUTnBUF is available for the 8051 to read. USB OUT tokens for the endpoint are
NAKd while BSY=1 (the 8051 is still reading data from the OUT endpoint).
A 1-to-0 transition of BSY (indicating that the 8051 can access the buffer) generates an
interrupt request for the OUT endpoint. After the 8051 reads the data from the OUT end-
point buffer, it loads the endpoint’s byte count register with any value to re-arm the end-
point, which automatically sets BSY=1. This enables the OUT transfer of data from the
host in response to the next OUT token. The CPU should never read endpoint data while
BSY=1.
Bit 0:
OUTnSTL OUT Endpoint (1-7) Stall
The 8051 sets this bit to “1” to stall an endpoint, and to “0” to clear a stall.
When the stall bit is “1,” the EZ-USB core returns a STALL Handshake for all requests to
the endpoint. This notifies the host that something unexpected has happened.
The 8051 sets an endpoint’s stall bit under two circumstances:
1. The host sends a “Set_Feature—Endpoint Stall” request to the specific endpoint.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-35
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