If the CONTROL transfer uses an OUT data phase, the 8051 must load a dummy byte
count into OUT0BC to arm the OUT endpoint buffer. Until it does, the EZ-USB core will
NAK the OUT tokens.
Bit 2:
INBSY
IN Endpoint Busy
INBSY is a read-only bit that is automatically cleared when a SETUP token arrives. The
8051 sets the INBSY bit by writing a byte count to IN0BC.
If the CONTROL transfer uses an IN data phase, the 8051 loads the requested data into the
IN0BUF buffer, and then loads the byte count into IN0BC to arm the data phase of the
CONTROL transfer. Alternatively, the 8051 can arm the data transfer by loading an
address into the Setup Data Pointer registers SUDPTRH/L. Until armed, the EZ-USB
core will NAK the IN tokens.
Bit 1:
HSNAK
Handshake NAK
HSNAK (Handshake NAK) is a read/write bit that is automatically set when a SETUP
token arrives. The 8051 clears HSNAK by writing a “1” to the register bit.
While HSNAK=1, the EZ-USB core NAKs the handshake (status) phase of the CON-
TROL transfer. When HSNAK=0, it ACKs the handshake phase. The 8051 can clear
HSNAK at any time during a CONTROL transfer.
Bit 0:
EP0STALL Endpoint Zero Stall
EP0STALL is a read/write bit that is automatically cleared when a SETUP token arrives.
The 8051 sets EP0STALL by writing a “1” to the register bit.
While EP0STALL=1, the EZ-USB core sends the STALL PID for any IN or OUT token.
This can occur in either the data or handshake phase of the CONTROL transfer.
Note
To indicate an endpoint stall on endpoint zero, set both EP0STALL and HSNAK bits.
Setting the EP0STALL bit alone causes endpoint zero to NAK forever because the host
keeps the control transfer pending.
Page 12-30
Chapter 12. EZ-USB Registers
EZ-USB TRM v1.9
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