IBNIRQ
IN Bulk NAK Interrupt Requests
7FB0
b7
b6
b5
b4
b3
b2
b1
b0
-
EP6IN
EP5IN
EP4IN
EP3IN
EP2IN
EP1IN
EP0IN
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
* AN2122/AN2126 only.
Figure 12-22. IN Bulk NAK Interrupt Request Register
These bits are set when a bulk IN endpoint (0-6) received an IN token while the endpoint
was not armed for data transfer. In this case the SIE automatically sends a NAK response,
and sets the corresponding IBNIRQ bit. If the IBN interrupt is enabled (USBIEN.5=1),
and the endpoint interrupt is enabled in the IBNIEN register, an interrupt is request gener-
ated. The 8051 can test the IBNIRQ register to determine which of the endpoints caused
the interrupt. The 8051 clears an IBNIRQ bit by writing a “1” to it.
IBNIEN
IN Bulk NAK Interrupt Enables
7FB1
b7
b6
b5
b4
b3
b2
b1
b0
-
EP6IN
EP5IN
EP4IN
EP3IN
EP2IN
EP1IN
EP0IN
R/W
x
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Figure 12-23. IN Bulk NAK Interrupt Enable Register
Each of the individual IN endpoints may be enabled for an IBN interrupt using the IBNEN
register. The 8051 sets an interrupt enable bit to 1 to enable the corresponding interrupt.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-27
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