BPADDRH
Breakpoint Address High
7FB2
b7
b6
b5
b4
b3
b2
b1
b0
A15
A14
A13
A12
A11
A10
A9
A8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
BPADDRL
Breakpoint Address Low
7FB3
b7
b6
b5
b4
b3
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Figure 12-24. IN/OUT Interrupt Enable Registers
When the current 16-bit address (code or xdata) matches the BPADDRH/BPADDRL
address, a breakpoint event occurs. The BPPULSE and BPEN bits in the USBBAV regis-
ter control the action taken on a breakpoint event.
If the BPEN bit is “0,” address breakpoints are ignored. If BPEN is “1” and BPPULSE is
“1,” an 8 CLK24 wide pulse appears on the BKPT pin. If BPEN is “1” and BPPULSE is
“0,” the BKPT pin remains active until the 8051 clears the BREAK bit by writing “1” to it.
Page 12-28
Chapter 12. EZ-USB Registers
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
