USB registers starting at SETUPDAT. The EZ-USB core takes care of any re-tries if it
finds any errors in the SETUP data. These two interrupt request bits are set by the EZ-
USB core, and must be cleared by firmware.
An 8051 program responds to the SUDAV interrupt request by either directly inspecting
the eight bytes at SETUPDAT or by transferring them to a local buffer for further process-
ing. Servicing the SETUP data should be a high 8051 priority, since the USB Specifica-
tion stipulates that CONTROL transfers must always be accepted and never NAKd. It is
therefore possible that a CONTROL transfer could arrive while the 8051 is still servicing
a previous one. In this case the previous CONTROL transfer service should be aborted
and the new one serviced. The SUTOK interrupt gives advance warning that a new CON-
TROL transfer is about to over-write the eight SETUPDAT bytes.
If the 8051 stalls endpoint zero (by setting the EP0STALL and HSNAK bits to 1), the EZ-
USB core automatically clears this stall bit when the next SETUP token arrives.
Like all EZ-USB interrupt requests, the SUTOKIR and SUDAVIR bits can be directly
tested and reset by the CPU (they are reset by writing a “1”). Thus, if the corresponding
interrupt enable bits are zero, the interrupt request conditions can still be directly polled.
Figure 7-3 shows the EZ-USB registers that deal with CONTROL transactions over EP0.
Registers Associated with Endpoint Zero
For handling SETUP transactions
Initialization
Data transfer
SETUPDAT
8 Bytes of
SETUP Data
T
D
USBIEN
USBIRQ
Global Enable:
T=Setup Token SUTOKIE
D=Setup Data SUDAVIE
Interrupt Control
15 14 13 12 11 10
9
1
8
0
SUDPTRH
SUDPTRL
T
D
Interrupt Request:
T=Setup Token SUTOKIR
D=Setup Data SUDAVIR
7
6
5
4
3
2
Figure 7-3. Registers Associated with EP0 Control Transfers
These registers augment those associated with normal bulk transfers over endpoint zero,
which are described in Chapter 6, "EZ-USB Bulk Transfers."
Page 7-4
Chapter 7. EZ-USB CPU
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
