7.2
Control Endpoint EP0
SETUP Stage
S
E
T
U
P
D
A
T
A
0
C
A
D
D
R
E
N
D
P
C
R
C
5
8 bytes
Setup
Data
R
C
1
A
C
K
6
Token Packet
Data Packet
H/S Pkt
SUTOK Interrupt
Core sets HSNAK=1
SUDAV Interrupt
DATA Stage
D
D
A
T
A
0
C
R
C
1
C
R
C
1
A
D
D
R
E
C
R
C
5
A
E
N
D
P
C
R
C
5
A
T
A
1
A
C
K
A
C
K
I
N
N
D
P
Payload
Data
I
N
D
D
R
Payload
Data
6
6
Data Packet
Token Packet
Data Packet
Token Packet
H/S Pkt
H/S Pkt
EP0-IN Interrupt
EP0-IN Interrupt
STATUS Stage
D
A
T
A
D
C
S
C
R
C
1
A
D
D
R
E
N
D
P
C
R
C
5
A
D
D
R
E
N
D
P
C
R
C
5
N
A
K
O
U
T
O
U
T
A
T
A
1
R
A
C
K
Y
N
C
C
1
....
1
6
6
Token Packet
Token Packet
H/S Pkt
Data Pkt
Data Pkt H/S Pkt
8051 clears HSNAK bit (writes 1 to it)
or sets the STALL bit.
Figure 7-1. A USB Control Transfer (This One Has a Data Stage)
Endpoint zero accepts a special SETUP packet, which contains an 8-byte data structure
that provides host information about the CONTROL transaction. CONTROL transfers
include a final STATUS phase, constructed from standard PIDs (IN/OUT, DATA1, and
ACK/NAK).
Some CONTROL transactions include all required data in their 8-byte SETUP Data
packet. Other CONTROL transactions require more OUT data than will fit into the eight
bytes, or require IN data from the device. These transactions use standard bulk-like trans-
fers to move the data. Note in Figure 7-1 that the “DATA Stage” looks exactly like a bulk
transfer. As with BULK endpoints, the endpoint zero byte count registers must be loaded
to ACK the data transfer stage of a CONTROL transfer.
Page 7-2
Chapter 7. EZ-USB CPU
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
