欢迎访问ic37.com |
会员登录 免费注册
发布采购

AN2131QC 参数 Datasheet PDF下载

AN2131QC图片预览
型号: AN2131QC
PDF下载: 下载PDF文件 查看货源
内容描述: 在EZ - USBTM集成电路 [The EZ-USBTM Integrated Circuit]
分类和应用:
文件页数/大小: 334 页 / 1468 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号AN2131QC的Datasheet PDF文件第118页浏览型号AN2131QC的Datasheet PDF文件第119页浏览型号AN2131QC的Datasheet PDF文件第120页浏览型号AN2131QC的Datasheet PDF文件第121页浏览型号AN2131QC的Datasheet PDF文件第123页浏览型号AN2131QC的Datasheet PDF文件第124页浏览型号AN2131QC的Datasheet PDF文件第125页浏览型号AN2131QC的Datasheet PDF文件第126页  
7 EZ-USB Endpoint Zero  
7.1  
Introduction  
Endpoint Zero has special significance in a USB system. It is a CONTROL endpoint, and  
is required by every USB device. Only CONTROL endpoints accept special SETUP  
tokens that the host uses to signal transfers that deal with device control. The USB host  
sends a repertoire of standard device requests over endpoint zero. These standard requests  
are fully defined in Chapter 9 of the USB Specification. This chapter describes how the  
EZ-USB chip handles endpoint zero requests.  
Because the EZ-USB chip can enumerate without firmware (see Chapter 5, "EZ-USB  
Enumeration and ReNumeration "), the EZ-USB core contains logic to perform enumer-  
ation on its own. This hardware assist of endpoint zero operations is make available to the  
8051, simplifying the code required to service device requests. This chapter deals with  
8051 control of endpoint zero (ReNum=1, Chapter 5), and describes EZ-USB resources  
such as the Setup Data Pointer that simplify 8051 code that handles endpoint zero  
requests.  
Endpoint zero is the only CONTROL endpoint in the EZ-USB chip. Although CON-  
TROL endpoints are bi-directional, the EZ-USB chip provides two 64-byte buffers,  
IN0BUF and OUT0BUF, which the 8051 handles exactly like bulk endpoint buffers for  
the data stages of a CONTROL transfer. A second 8-byte buffer, SETUPDAT, which is  
unique to endpoint zero, holds data that arrives in the SETUP stage of a CONTROL trans-  
fer. This relieves the 8051 programmer of having to keep track of the three CONTROL  
transfer phases—SETUP, DATA, and STATUS. The EZ-USB core also generates separate  
interrupt requests for the various transfer phases, further simplifying code.  
The IN0BUF and OUT0BUF buffers have two special properties that result from being  
used by CONTROL endpoint zero:  
Endpoints 0-IN and 0-OUT are always valid, so the valid bits (LSB of IN07VAL  
and OUT07VAL registers) are permanently set to 1. Writing any value to these  
two bits has no effect, and reading these bits always returns a 1.  
Endpoint 0 cannot be paired with endpoint 1, so there is no pairing bit in the USB-  
PAIR register for endpoint 0 or 1.  
EZ-USB TRM v1.9  
Chapter 7. EZ-USB CPU  
Page 7-1  
 复制成功!