P R E L I M I N A R Y
pSRAM ADDRESS SKEW
over 10 µs
CE#1
WE#
Address
tRC min
Figure 35. Read Address Skew
Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 µs, at least one valid address
cycle over tRC min is required during that period.
over 10 µs
CE#1
tWP min
WE#
Address
tWC min
Figure 36. Write Address Skew
Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 µs, at least one valid address
cycle over tWC min, in addition to tWP min, is required during that period.
July 19, 2002
Am49DL32xBG
61
CYPRESS [ CYPRESS ]
