P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Write Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
50
60
60
85
85
60
70
70
tWC
tWP
tCW
tBW
tAS
Write Cycle Time
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Time
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Min
Min
Min
Max
Min
Min
Min
Min
0
0
tWR
tODW
tOEW
tDS
Write Recovery Time
WE# Low to Write to Output High-Z
WE# High to Write to Output Active
Data Set-up Time
20
0
30
0
tDH
Data Hold from Write Time
CE2 Hold Time
ns
µs
tCH
300
tWC
Addresses
A0 to A20
tAS
tWR
tWP
WE#
tCW
CE#1
CE2
tCH
tBW
LB#, UB#
tODW
tOEW
(Note 3)
(Note 4)
High-Z
DOUT
I/O1 to 16
tDH
tDS
DIN
I/O1 to 16
(Note 1)
Valid Data In
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 30. Pseudo SRAM Write Cycle—WE# Control
56
Am49DL32xBG
July 19, 2002
CYPRESS [ CYPRESS ]
