P R E L I M I N A R Y
pSRAM DATA RETENTION
Parameter
Parameter Description
Symbol
Min
Typ
Max
3.3
70
Unit
V
Test Setup
VDR
IDR
VCC for Data Retention
Data Retention Current
CS1#s ≥ VCC – 0.2 V (Note 1)
2.7
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
1.0
(Note 2)
µA
tCS
tCH
CE2 Setup Time
0
300
10
0
ns
µs
ms
ns
µs
CE2 Hold Time
tDPD
tCHC
tCHP
CE2 Pulse Width
CE2 Hold from CE#1
CE2 Hold from Power On
30
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled).
2. Typical values are not 100% tested.
pSRAM POWER ON AND DEEP POWER DOWN
CE#1
tDPD
CE#2
tcs
tCH
Figure 33. Deep Power-down Timing
Note: Data cannot be retained during deep power-down standby mode.
VDD min
VDD
tCHC
CE#1
tCHP
tCH
CE#2
Figure 34. Power-on Timing
60
Am49DL32xBG
July 19, 2002
CYPRESS [ CYPRESS ]
