P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Read Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
70
70
85
85
85
85
tRC
tACC
tCO
tOE
Read Cycle Time
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Max
Max
Max
Max
Min
Min
Min
Max
Max
Max
Min
Min
Min
Max
Min
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold from Address Change
Page Mode Time
25
25
10
0
tBA
tCOE
tOEE
tBE
0
tOD
tODO
tBD
20
20
20
10
70
30
30
10
tOH
tPM
tPC
Page Mode Cycle Time
tAA
Page Mode Address Access Time
Page Output Data Hold Time
tAOH
tRC
Addresses
A0 to A20
tACC
tOH
tCO
CE#1
Fixed High
CE2
OE#
tOD
tOE
tODO
WE#
tBA
LB#, UB#
tBE
tOEE
tBD
Indeterminate
High-Z
High-Z
D
OUT
Valid Data Out
I/O1 to 16
tCOE
Notes:
1. tOD, tODo, tBD, and tODW are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
Figure 28. Psuedo SRAM Read Cycle
54
Am49DL32xBG
July 19, 2002
CYPRESS [ CYPRESS ]
