ACM100
The bits are defined as follows:
[15:12] Reserved:
Reserved for future use
The first time this field is written after a power on or reset (including a soft reset initiated by writing
to register 0xF) the Q value will be stored in the table at the location for gray code 0. The second
write will store the Q value into location 1 and subsequent writes will continue to increment the
storage location. The algorithm uses 512 locations.
[11:0] Q:
0x0D Video Status (Read Only)
Bit Definition
8
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
Reserved
CUR_GAMMA
IMAG_AV
The Video Status register is a read only register that provides the status of the current image to the user.
The bits are defined as follows:
[15:13] Reserved:
These bits are reserved for future use and should not be set. To ensure compatibility with future
releases, we recommend using a read/modify/write operation to preserve the status of these bits.
This bit field represents the current gamma code most recently calculated by the Autobrite
algorithm. This value is updated as soon as the new value is calculated and there is a two frame
latency before they take effect.
[12:8] CUR_GAMMA:
[7:0] IMAG_AV:
This bit field represents the current image average most recently calculated by the Autobrite
algorithm.
0x0F Firmware Version/Soft Reset
Bit Definition
8
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
Definition When Read
HW_Ver
PCB_Ver
RTL_Maj_Ver
RTL_Min_Ver
Definition When Written
Reserved
When read, the Firmware Version/Soft Reset register is used to determine the revision status of the camera. When written, the
register is used to reset the camera. The following defines the fields of this register:
Read
[15:12] PCB_Ver:
This field reads back the revision level of the PCB. It is incremented each time the artwork is
changed on the PCB in the camera.
This field reads back the hardware version of the camera. It starts at zero with each PCB version
and is incremented as changes are made to the hardware that do not affect the PCB artwork.
[11:8] HW_Ver:
This field reads back the major revision code for the firmware in the FPGA. This field is
independent of the PCB and HW versions and is incremented each time a major change to the
functionality of the FPGA is implemented.
[7:4] RTL_Maj_Ver:
This field is reset each time the RTL_Maj_Ver field changes and is incremented each time the
firmware is changed.
[3:0] RTL_Min_Ver:
Write
These bits are reserved for future use and should not be set. Write ‘0’s to this field.
Writing a ‘1’ to this bit will return all registers to the power on state.
[15:1] Reserved:
[0] RST:
Document Number: 001-05325 Rev. **
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