CY7C1359A/GVT71256T18
Functional Block Diagram—256Kx18[1]
HIGHER BYTE
WRITE
WEH#
BWE#
D
Q
D
Q
LOWER BYTE
WRITE
WEL#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
Latch
CE2#
ZZ
Power Down Logic
OE#
MATCH
D
Q
ADSP#
MOE#
Compare
Input
Register
DEN#
Latch
CLK
16
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQ1-
DQ18
D
Q
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05120 Rev. **
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