Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37256V
1 4 0
1 2 0
1 0 0
8 0
H ig h S p e e d
L o w P o w e r
6 0
4 0
2 0
0
0
2 0
4 0
6 0
F re q u e n c y (M H z )
8 0
1 0 0
1 2 0
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 3.3V, T = Room Temperature
V
CC
A
CY37384V
200
180
160
140
120
100
80
H igh S peed
Low P ow er
60
40
20
0
0
10
20
30
40
50
60
70
80
90
F req u e n cy (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 3.3V, T = Room Temperature
V
CC
A
Document #: 38-03007 Rev. *D
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