Ultra37000 CPLD Family
Typical 3.3V Power Consumption
CY37032V
30
High Speed
25
20
15
10
5
Low Power
0
0
20
40
60
80
100
120
140
160
Frequency (MHz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
= 3.3V, T = Room Temperature
A
CC
CY37064V
45
40
35
30
25
20
15
10
5
High Speed
Low Power
0
0
20
40
60
80
100
120
140
Frequency (MHz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 3.3V, T = Room Temperature
V
CC
A
Document #: 38-03007 Rev. *D
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