4.0 Registers
RS8953B/8953SPB
4.6 PCM Formatter
HDSL Channel Unit
0xC0—TSER Frame Bit Location (TFRAME_LOC_LO)
TFRAME_LOC and TMF_LOC work in conjunction to define the location of bit 0, frame 0, at the TSER data
input with respect to TMSYNC.
7
6
5
4
3
2
1
0
TFRAME_LOC[7:0]
0xC1—TSER Frame Bit Location (TFRAME_LOC_HI)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TFRAME_LOC[8]
TFRAME_LOC[8:0] TSER Frame Bit Location—Establishes the number of PCM bit delays, in the range of 1 to 512
bits, from the rising edge of TMSYNC until PCM bit 0 is sampled on TSER. A value of 0
delays TMSYNC by three TCLK periods. If TMSYNC and TSER are input aligned, where
TMSYNC’s rising edge coincides with TSER input of PCM bit 0, then TFRAME_LOC is
programmed to equal the PCM frame length minus three. The following examples assume
TMSYNC and TSER are input aligned:
PCM Frame Length
E1 = 256 bits
TFRAME_LOC[8:0] = Decimal (hex)
253 (0x0FD)
T1 = 193 bits
190 (0x0BE)
64x64 = 512 bits
509 (0x1FD)
0xC2—TSER Multiframe Bit Location (TMF_LOC)
7
6
5
4
3
2
1
0
—
—
TMF_LOC[5]
TMF_LOC[5:0]
TSER Multiframe Bit Location—TMF_LOC sets the number of frame delays, in the range of
1 to 64 frames, from TMSYNC (delayed by TFRAME_LOC) until PCM frame 0 is present on
TSER. A value of 0 delays TMSYNC by one PCM frame. If TMSYNC and TSER are input
aligned, TMF_LOC is programmed to equal the multiframe length minus two. The following
examples assume TMSYNC’s rising edge coincides with PCM frame 0 input on TSER:
PCM Multiframe Length
E1 = 16 frames
TMF_LOC[5:0] = Decimal (hex)
14 (0x0E)
SF = 12 frames
10 (0x0A)
ESF = 24 frames
22 (0x16)
0xC3—RSER Frame Bit Location (RFRAME_LOC_LO)
RFRAME_LOC and RMF_LOC work in conjunction to define which RSER bit and frame location is marked
by the RMSYNC output. Typically, RMSYNC is used as a PCM multiframe sync signal and is programmed to
mark during RSER output of bit0, frame0. However, any RSER bit location within the received multiframe can
be marked as desired.
4-26
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
