RS8953B/8953SPB
3.0 Circuit Descriptions
HDSL Channel Unit
3.6 PRA Function
Enabling the CRC4 generator causes CRC4 regeneration of the E1 data
(RSER). The result is inserted into the data stream in the appropriate location in
accordance with the CRC4 procedure specified in CCITT recommendation
G.704.
If the CRC4 generator is disabled, the following options are available: New
values are inserted for the CRC4 bits, or you can leave the CRC4 bits untouched.
If new values are inserted, an external CPU must be used to program the value of
these bits. To implement this, a simple storage register can be used to insert four
bits into the data stream. The CRC4 insertion is repeated each E1 frame until
another value is programmed, or until another mode is selected.
3.6.2 Definitions of Detection Algorithms
When transferring data from HDSL or RSER, the following definitions of
detection algorithms apply:
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•
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Normal operational frames: The algorithm will be in accordance with
CCITT Recommendation G.706[7]. This condition is indicated by one bit
in a register.
Loss of frame alignment: The algorithm will be in accordance with CCITT
Recommendation G.706[7]. This condition is indicated by one bit in a
register.
Code words: Code words consist of four SA6 bits and the A-bit. A new
code is declared only when the value of the SA6 bits and the A-bit remains
the same in the last eight frames. The code word is then stored in a 5-bit
register.
3.6.3 Inserting Data Transferred from HDSL to RSER
When transferring data from HDSL to RSER, bits are transferred in the following
manner:
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•
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Each A-bit and SA4, SA5, SA7, and SA8 bit may be selected as
transparent or non-transparent. For non-transparent bits, the new value of
the certain bit is stored in a register and is inserted into the correct location
of the data stream (RSER).
The SA6 bits may be transferred either transparently or non-transparently.
Selecting transparent or non-transparent affects all four SA6 bits. For
non-transparent transfers, the new value of the bits is stored in a register
and is inserted into the correct location of the data stream (RSER).
The FAS bits may be transferred either transparently or non-transparently.
Selecting transparent or non-transparent affects all the FAS bits. For
non-transparent bits, the FAS value is inserted into the correct location of
the data stream (RSER).
3.6.4 Transferring Data from TSER to HDSL
When CRC4 monitoring is enabled, data received from TSER is checked for error
blocks by using the CRC4 procedure, as specified in CCITT recommendation
G.704[9], subclause 2.3.3. The check result, reflected by the E-bits, is inserted
into the correct location of the data stream.
N8953BDSB
Conexant
3-35
CONEXANT [ CONEXANT SYSTEMS, INC ]
