4.0 Registers
RS8953B/8953SPB
HDSL Channel Unit
Register Types
The Microprocessor Unit (MPU) must read and write real-time registers, and
receive and transmit EOC, IND, Z-bit, and status registers within a prescribed
time interval (1–6 ms) after their respective HDSL channel’s 6 ms frame
interrupt. This must be done to avoid reading or writing transitory data values.
Failure to read real-time registers within the prescribed interval results in a loss of
data.
The MPU writes to non-real time command registers which are event-driven
and which are written when the system initializes, changes modes, or responds to
an error condition. Whenever data is written to a RS8953B register, the data is
first written to the Shadow Write Register [SHADOW_WR; addr 0x3B], and then
the data is transferred from the SHADOW_WR register to the addressed register.
For diagnostics, software can read-verify the last write cycle by reading the
SHADOW_WR register. This will confirm that the data was written to the
SHADOW_WR register, but does not confirm that the data was transferred to the
addressed register. If the Write Pulse Width specification is not met, then the data
may not be correctly transferred from the SHADOW_WR register to the
addressed register. To prevent transitory write data in non-real time command
registers, the MPU can first write the desired data value to the SHADOW_WR
register, and then write the same data to the desired register.
MPU reads may be interrupt event driven, polled, or a combination of both,
thereby allowing the choice to be dictated by system architecture. Polled
procedures can avoid reading transitory real-time data by monitoring the Interrupt
Request Register [IRR; address 0x1F] bits to determine when a particular group
of registers has been updated. Interrupt driven and polled procedures must
complete reading within the prescribed 1–6 ms interval following HDSL frame
interrupts.
Register Groups
RS8953B command, status, and real-time registers are divided into three groups:
Common, Transmit, and Receive registers. Common registers effect overall
operation, primarily the PCM channel and the DPLL. Three identical groups of
Transmit and Receive registers only affect operation or report status of the
respective HDSL channel. Transmit registers reference data flow from the PCM
channel to the HDSL channel outputs, while Receive registers reference data flow
from the HDSL channel to the PCM channel outputs. RS8953B initialization and
error handling routines, written in C-language, are available via the terms of the
HDSL software license agreement.
The addresses shown for each Transmit and Receive register or bit description
reference only HDSL Channel 1. (See the Summary tables at the start of each
section to find address locations for HDSL channels 2 and 3.)
4-2
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
