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RS8953BEPJ 参数 Datasheet PDF下载

RS8953BEPJ图片预览
型号: RS8953BEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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RS8953B/8953SPB  
3.0 Circuit Descriptions  
HDSL Channel Unit  
3.5 HDSL Channel  
After entering In Sync, the framer either remains In Sync as successive sync  
words are detected, or regresses to the Sync Errored state if sync pattern errors are  
found. During Sync Errored states, the number of matching bits from each  
comparison of received sync word and programmed sync word patterns must  
meet or exceed the programmed pattern match tolerance specified by  
THRESH_CORR [RCMD_2; addr 0x61]. If the number of matching bits falls  
below tolerance, the framer expands the locations searched to quats on either side  
of the expected location, as shown in Figure 3-24. After detecting a sync pattern  
error and changing to the Sync Errored state, the framer passes through a  
programmable number of intermediate Sync Errored states, before entering the  
Out Of Sync state. STATE_CNT increments for each frame in which sync is not  
detected until the count reaches the LOSS_SYNC criteria [RCMD_1; addr 0x60]  
and the framer enters the Out Of Sync state. If at any time during the Sync  
Errored state the framer detects a completely correct sync word pattern at one of  
the valid frame locations, then the framer returns to the In Sync state. The ETSI  
standard recommends the REACH_SYNC = 2 and LOSS_SYNC = 6 framing  
criteria.  
Figure 3-24. Threshold Correlation Effect on Expected Sync Locations  
SYNC Pattern THRESH_CORR  
SYNC_ERRORED  
1
SYNC_ERRORED  
2
SYNC_ERRORED  
3
–1q +1q  
–1q +1q  
–1q +1q  
T
0
6 ms  
12 ms  
18 ms  
SYNC Pattern < THRESH_CORR  
SYNC_ERRORED  
1
SYNC_ERRORED  
SYNC_ERRORED  
2
3
–2q +2q  
–3q –1q +1q +3q  
12 ms  
–4q –2q  
+2q+4q  
T
0
6 ms  
18 ms  
q = 2 Bits = 1 Quat  
= Search Location  
3.5.2.3 Descrambler  
The descrambler operates at the BCLKn bit rate on all HDSL receive data, except  
for the 14-bit SYNC words and 4 STUFF bits. The MPU enables the descrambler  
by setting the DSCR_EN bit and selects the descrambler algorithm via  
DSCR_TAP [RCMD_2; addr 0x61]. Two descrambling algorithms are  
implemented as follows:  
In the HTU-R to HTU-C direction, the polynomial shall be  
–23  
–18  
X
X
1, where is equal to modulo 2 summation.  
In the HTU-C to HTU-R direction, the polynomial shall be  
–23  
–5  
X
X
1, where is equal to modulo 2 summation.  
N8953BDSB  
Conexant  
3-31  
 
 
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