3.0 Circuit Descriptions
RS8953B/8953SPB
3.5 HDSL Channel
HDSL Channel Unit
3.5.2 HDSL Receive
The RS8953B contains three identical HDSL receivers, each receiver the same as
the one shown in Figure 3-22. The receiver is responsible for frame alignment,
destuffing, overhead extraction, descrambling of payload data, error performance
monitoring, and payload mapping of HDSL data from received frames into the
RFIFO. The receive framer monitors incoming HDSL data to locate SYNC words
and to identify frame boundaries for use by other circuits that locate and remove
bit stuffing, to check CRC errors, to extract HOH bits and to map payload data to
the RFIFO. One of the receivers is configured to act as master reference for the
PCM receive channel and from which T1 framing bits are extracted (see
MASTER_SEL, CMD_5; addr 0xE9). The master channel also supplies its 6 ms
frame reference for DPLL clock recovery.
Figure 3-22. HDSL Receiver Block Diagram
HDSL Framer
State
CNT
SYNC
Detect
CHn RSYNC
STUFF
Detect
CRC
CHK
HOH
Demux
HFRAME
Count
ROHn
BCLKn
RAUXn
QCLKn
RDATn
2B1Q
Decoder
Data to
RFIFO
Payload
Map
Descrambler
TDATn
PH_LOOP
= Command Register Bit
3.5.2.1 2B1Q Decoder
The 2B1Q decoder provides the capability to directly connect to the Conexant
HDSL transceiver. The 2B1Q decoder samples and aligns the incoming sign and
magnitude data. (Refer to Table 3-6 for 2B1Q mapping.) All three HDSL
channels operate independent of one another to allow separate, asynchronous
clock signals, to be applied from the system at each HDSL interface.
Table 3-6. 2B1Q Decoder Alignment
First Bit
(Sign)
Second Bit
(Magnitudes)
Quaternary Symbol
(Quat)
1
1
0
0
0
1
1
0
+3
+1
–1
–3
3-28
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
