RS8953B/8953SPB
6.0 Electrical and Timing Specifications
HDSL Channel Unit
6.1 Absolute Maximum Ratings
6.1.5 MPU Interface Timing
Motorola- (MPUSEL = 1) and Intel- (MPUSEL = 0) style microprocessor bus
timing, as follows:
Table 6-9. MPU Interface Timing Requirements
Symbol
Parameter
Minimum
Maximum
Units
1
2
ALE Pulse-Width High
20
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Input Setup to ALE Falling
Address Input Hold after ALE Low
Data Input Setup to End of Write Pulse
Data Input Hold After Write Pulse
WR* Setup to Start of Read or Write Pulse
WR* Hold after Read or Write Pulse
ALE Hold after Read or Write Pulse
3
5
10
8
6
7
10
10
8
8
9
10
Write Pulse-Width:
1
--------------
2 ×
2 ×
WR*, RD*, and CS* Low (MPUSEL = 1)
RD* = 1, WR*, and CS* Low (MPUSEL = 0)
fGCLK
11
Read Pulse Width (WR* = 1, RD* and CS* Low)
26
ns
ns
Read Pulse Width (WR* = 1, RD* and CS* Low)
Address = 0x3C only.
1
--------------
fGCLK
Table 6-10. MPU Interface Switching Characteristics
Symbol
Parameter
Minimum
Maximum
Units
12
13
14
15
16
Data Out Enable (Low Z) after Start of Read Pulse
Data Out Valid After Start of Read Pulse (Access Time)
Data Out Hold After End of Read Pulse
2
ns
ns
ns
ns
ns
26
25
1
5
Data Out Disable (High Z) after End of Read Pulse
INTR* Hold After End of Write Pulse
(when writing interrupt mask or clear registers)
17
INTR* Delay from End of Write Pulse
20
ns
(when writing interrupt mask or enable registers)
N8953BDSB
Conexant
6-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
