6.0 Electrical and Timing Specifications
RS8953B/8953SPB
6.1 Absolute Maximum Ratings
HDSL Channel Unit
Table 6-5. Data Timing Requirements
Symbol
Parameter
Minimum
Maximum
Units
Ts
Input Setup Time
Input Hold Time
35
10
ns
ns
Thld
Table 6-6. Input Clock Edge Selection
TCLK_SEL
(CMD_2)
RCLK_SEL
(CMD_2)
RCLK_INV
(CMD_7)
Clock
Edge
Inputs
HDSL Channel Inputs
BCLK1
BCLK2
BCLK3
Falling
Falling
Falling
QCLK1, RDAT1, TAUX1
—
QCLK2, RDAT2, TAUX2
QCLK3, RDAT3, TAUX3
PCM Channel Inputs
TCLK
TCLK
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
TSER, INSDAT, TMSYNC
00
01
1x
1x
1x
1x
1x
1x
—
—
00
00
01
01
10
10
—
—
0
RCLK
RCLK
1
EXCLK
EXCLK
EXCLK
EXCLK
0
1
0
1
Test Access Inputs
TMS, TDI
TCK
Rising
—
6-4
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
