RS8953B/8953SPB
6.0 Electrical and Timing Specifications
HDSL Channel Unit
6.1 Absolute Maximum Ratings
6.1.3 Timing Requirements
Figure 6-1. Input Clock Timing
Input Clock
Tf
Tr
Th
Tl
Tp
Table 6-4. Clock Timing Requirements
Symbol
Parameter
Minimum
Maximum
Units
1/ Tp
Mclk Frequency (Pll_dis = 0; Pll_mul = 16)
Mclk Frequency (Pll_dis = 0; Pll_mul = 8)
Mclk Frequency (Pll_dis = 1)
Tclk, Exclk Frequency
Bclkn Frequency
3.75
7.5
5.0
10
MHz
MHz
MHz
MHz
MHz
MHz
ns
60
80
0.128
0.144
0
4.096
2.320
25
Tck Frequency
Th
Tl
Clock Width High
0.4 x TP
0.4 x TP
0.6 x TP
0.6 x TP
20
Clock Width Low
ns
Tr
Clock Rise Time
ns
Tf
Clock Fall Time
20
ns
Figure 6-2. Input Setup and Hold Timing
Input Clock
Ts
Thld
Falling Edge
Input Sample
Ts
Thld
Rising Edge
Input Sample
N8953BDSB
Conexant
6-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
