6.0 Electrical and Timing Specifications
RS8953B/8953SPB
6.1 Absolute Maximum Ratings
HDSL Channel Unit
Table 6-8. Output Clock Edge Selection
TCLK_SEL
(CMD_2)
RCLK_SEL
(CMD_2)
RCLK_INV
(CMD_7)
Clock
Edge
Outputs
HDSL Channel Outputs
BCLK1
BCLK2
BCLK3
Rising
Rising
Rising
TDAT1, TLOAD1, RAUX1, ROH1
TDAT2, TLOAD2, RAUX2, ROH2
TDAT3, TLOAD3, RAUX3, ROH3
—
PCM Transmit Channel Outputs
TCLK
TCLK
Rising
Falling
Rising
Falling
Rising
Falling
MSYNC, INSERT
MSYNC, INSERT
MSYNC, INSERT
MSYNC, INSERT
MSYNC, INSERT
MSYNC, INSERT
00
01
1x
1x
1x
1x
—
—
00
00
01
10
—
—
0
RCLK
RCLK
EXCLK
EXCLK
1
0
0
PCM Receive Channel Outputs
RCLK
RCLK
EXCLK
EXCLK
TCLK
Rising
Falling
Rising
Falling
Rising
Falling
RSER, RMSYNC, DROP
RSER, RMSYNC, DROP
RSER, RMSYNC, DROP
RSER, RMSYNC, DROP
RSER, RMSYNC, DROP
RSER, RMSYNC, DROP
—
—
—
—
00
01
00
00
01
10
11
11
0
1
0
0
0
0
TCLK
Test Access Outputs
TDO
TCK
Falling
—
6-6
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
