CX82100 Home Network Processor Data Sheet
Table 16-2. CX82100 Interface Registers Sorted by Supported Function (Continued)
Register Label
Register Name
Host Interface Registers
Host Control Register
ASB Address
Type
RW
Default Value
Ref.
5.3.1
HST_CTRL
0x002D0000
0x002D0004
0x00000008
0x00739CE7
HST_RWST
HST_WWST
Host Master Mode Read-Wait-State Control
RW
5.3.2
Register
Host Master Mode Write-Wait-State Control
Register
0x002D0008
RW
0x00739CE7
5.3.3
HST_XFER_CNTL
HST_READ_CNTL1
HST_READ_CNTL2
HST_WRITE_CNTL1
HST_WRITE_CNTL2
MSTR_INTF_WIDTH
MSTR_HANDSHAKE
HDMA_SRC_ADDR
HDMA_DST_ADDR
HDMA_BCNT
Host Master Mode Transfer Control Register
Host Master Mode Read Control Register 1
Host Master Mode Read Control Register 2
Host Master Mode Write Control Register 1
Host Master Mode Write Control Register 2
Host Master Mode Peripheral Size
Host Master Mode Peripheral Handshake
Host Master Mode DMA Source Address
Host Master Mode DMA Destination Address
Host Master Mode DMA Byte Count
0x002D000C
0x002D0010
0x002D0014
0x002D0018
0x002D001C
0x002D0020
0x002D0024
0x002D0028
0x002D002C
0x002D0030
0x002D0034
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
HDMA_TIMERS
Host Master Mode DMA Timers
External Memory Control Register
EMCR
External Memory Control Register
0x00350010
RW
0x00000000
6.12.1
EMAC Registers
E_DMA_1
E_NA_1
E_Stat_1
E_IE_1
EMAC 1 Source/Destination DMA Data Register
EMAC 1 Network Access Register
EMAC 1 Status Register
EMAC 1 Interrupt Enable Register
EMAC 1 Receiver Last Packet Register
EMAC 1 MII Management Interface Register
EMAC 1 Destination DMA Data Register
EMAC 2 Source/Destination DMA Data Register
EMAC 2 Network Access Register
EMAC 2 Status Register
EMAC 2 Interrupt Enable Register
EMAC 2 Receiver Last Packet Register
EMAC 2 MII Management Interface Register
EMAC 2 Destination DMA Data Register
USB Registers
0x00310000
0x00310004
0x00310008
0x0031000C
0x00310010
0x00310018
0x00310020
0x00320000
0x00320004
0x00320008
0x0032000C
0x00320010
0x00320018
0x00320020
RWp
RW
RW*
RW
RW*
RW1
ROp
RWp
RW
RW*
RW
RW*
RW2
ROp
(don’t care)
0x80200000
0x00000000
0x00000000
0x00000000
0x00000008
(don’t care)
(don’t care)
0x80200000
0x00000000
0x00000000
0x00000000
0x00000008
(don’t care)
7.11.1
7.11.3
7.11.4
7.11.6
7.11.5
7.11.7
7.11.2
7.11.1
7.11.3
7.11.4
7.11.6
7.11.5
7.11.7
7.11.2
E_LP_1
E_MII_1
ET_DMA_1
E_DMA_2
E_NA_2
E_Stat_2
E_IE_2
E_LP_2
E_MII_2
ET_DMA_2
U0_DMA
U1_DMA
U2_DMA
U3_DMA
UT_DMA
U_CFG
U_IDAT
U_CTR1
U_CTR2
U_CTR3
U_STAT
U_IER
U_STAT2
U_IER2
EP0_IN_TX_INC
EP0_IN_TX_PEND
EP0_IN_TX_QWCNT
USB Source/Destination DMA Data Register 0
USB Source/Destination DMA Data Register 1
USB Source/Destination DMA Data Register 2
USB Source/Destination DMA Data Register 3
USB Destination DMA Data Register
USB Configuration Data Register
USB Interrupt Data Register
USB Control Register 1
USB Control Register 2
USB Control Register 3
USB Status
USB Interrupt Enable Register
USB Status Register 2
USB Interrupt Enable Register 2
EP0_IN Transmit Increment Register
EP0_IN Transmit Pending Register
EP0_IN Transmit qword Count Register
0x00330000
0x00330008
0x00330010
0x00330018
0x00330020
0x00330024
0x00330028
0x0033002C
0x00330030
0x00330034
0x00330038
0x0033003C
0x00330040
0x00330044
0x00330048
0x0033004C
0x00330050
RWp
RWp
RWp
RWp
RO
RW
RW
RW
RW
RW
RR
RW
RR
RW
RW
RO
(don’t care)
(don’t care)
(don’t care)
(don’t care)
(don’t care)
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.8.8
8.8.9
8.8.10
8.8.11
8.8.12
8.8.13
8.8.14
8.9.1
8.9.2
8.9.3
RO
1 Note: The bit E_MII_1[1] is Read Only.
2 Note: The bit E_MII_2[1] is Read Only.
101306C
Conexant Proprietary and Confidential Information
14-3
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