CX82100 Home Network Processor Data Sheet
14.3
Interface Registers Sorted by Address
The CX82100 interface registers sorted by address are listed in Table 14-3.
Table 14-3. CX82100 Interface Registers Sorted by Address
Register Label
HST_CTRL
HST_RWST
Register Name
Host Control Register
ASB Address
0x002D0000
0x002D0004
Type
RW
RW
Default Value
0x00000008
0x00739CE7
Ref.
5.3.1
5.3.2
Host Master Mode Read-Wait-State Control
Register
HST_WWST
Host Master Mode Write-Wait-State Control
Register
0x002D0008
RW
0x00739CE7
5.3.3
HST_XFER_CNTL
HST_READ_CNTL1
HST_READ_CNTL2
HST_WRITE_CNTL1
HST_WRITE_CNTL2
MSTR_INTF_WIDTH
MSTR_HANDSHAKE
HDMA_SRC_ADDR
HDMA_DST_ADDR
HDMA_BCNT
HDMA_TIMERS
DMAC_1_Ptr1
DMAC_2_Ptr1
DMAC_3_Ptr1
DMAC_4_Ptr1
Host Master Mode Transfer Control Register
Host Master Mode Read Control Register 1
Host Master Mode Read Control Register 2
Host Master Mode Write Control Register 1
Host Master Mode Write Control Register 2
Host Master Mode Peripheral Size
Host Master Mode Peripheral Handshake
Host Master Mode DMA Source Address
Host Master Mode DMA Destination Address
Host Master Mode DMA Byte Count
Host Master Mode DMA Timers
DMAC 1 Current Pointer 1
DMAC 2 Current Pointer 1
DMAC 3 Current Pointer 1
DMAC 4 Current Pointer 1
DMAC 5 Current Pointer 1
DMAC 6 Current Pointer 1
DMAC 7 Current Pointer 1
DMAC 8 Current Pointer 1
DMAC 9 Current Pointer 1
0x002D000C
0x002D0010
0x002D0014
0x002D0018
0x002D001C
0x002D0020
0x002D0024
0x002D0028
0x002D002C
0x002D0030
0x002D0034
0x00300000
0x00300004
0x00300008
0x0030000C
0x00300010
0x00300014
0x00300018
0x0030001C
0x00300020
0x00300024
0x00300028
0x0030002C
0x00300030
0x00300034
0x00300038
0x0030003C
0x00300040
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW*
RO
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
4.5.1
RW*
RO
DMAC_5_Ptr1
DMAC_6_Ptr1
DMAC_7_Ptr1
DMAC_8_Ptr1
RW*
RW*
RW*
RW*
RW*
RW*
RW*
DMAC_9_Ptr1
DMAC_10_Ptr1
DMAC_11_Ptr1
*** Reserved ***
DMAC_1_Ptr2
DMAC_2_Ptr2
DMAC_3_Ptr2
DMAC 10 Current Pointer 1
DMAC 11 Current Pointer 1
DMAC 1 Indirect/Return Pointer 2
DMAC 2 Indirect/Return Pointer 2
DMAC 3 Indirect/Return Pointer 2
DMAC 4 Indirect/Return Pointer 2
DMAC 5 Indirect/Return Pointer 2
RW*
RW*
RW*
RW*
RW*
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
4.5.4
4.5.4
4.5.4
4.5.4
4.5.4
DMAC_4_Ptr2
DMAC_5_Ptr2
*** Reserved ***
0x00300044–
0x0030005C
DMAC_1_Cnt1
DMAC_2_Cnt1
DMAC_3_Cnt1
DMAC_4_Cnt1
DMAC_5_Cnt1
DMAC_6_Cnt1
*** Reserved ***
DMAC 1 Buffer Size Counter 1
DMAC 2 Buffer Size Counter 1
DMAC 3 Buffer Size Counter 1
DMAC 4 Buffer Size Counter 1
DMAC 5 Buffer Size Counter 1
DMAC 6 Buffer Size Counter 1
0x00300060
0x00300064
0x00300068
0x0030006C
0x00300070
0x00300074
RW*
RW*
RW*
RW*
RW*
RW*
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
4.5.3
4.5.3
4.5.3
4.5.3
4.5.3
4.5.3
0x00300078–
0x0030007C
DMAC_9_Cnt1
DMAC_10_Cnt1
DMAC_11_Cnt1
*** Reserved ***
DMAC 9 Buffer Size Counter 1
DMAC 10 Buffer Size Counter 1
DMAC 11 Buffer Size Counter 1
0x00300080
0x00300084
0x00300088
RW*
RW*
RW*
0x00000000
0x00000000
0x00000000
4.5.3
4.5.3
4.5.3
0x0030008C–
0x00300090
DMAC_2_Cnt2
*** Reserved ***
DMAC_4_Cnt2
*** Reserved ***
DMAC 2 Buffer Size Counter 2
DMAC 4 Buffer Size Counter 2
0x00300094
0x00300098
0x0030009C
WO
WO
0x00000000
0x00000000
4.5.4
4.5.4
0x003000A0–
0x003000FC
14-6
Conexant Proprietary and Confidential Information
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