CX82100 Home Network Processor Data Sheet
Table 16-3. CX82100 Interface Registers Sorted by Address (Continued)
Register Label
DMAC_12_Ptr1
DMAC_13_Ptr1
*** Reserved ***
Register Name
DMAC 11 Current Pointer 1
DMAC 12 Current Pointer 1
ASB Address
0x00300100
0x00300104
Type
RW*
RW*
Default Value
0x00000000
0x00000000
Ref.
4.5.1
4.5.1
0x00300108–
0x0030010C
DMAC_12_Cnt1
DMAC_13_Cnt1
*** Reserved ***
DMAC 11 Buffer Size Counter 1
DMAC 12 Buffer Size Counter 1
0x00300110
0x00300114
RW*
RW*
0x00000000
0x00000000
4.5.3
4.5.3
0x00300118–
0x00300124
E_DMA_1
E_NA_1
E_Stat_1
E_IE_1
E_LP_1
E_MII_1
ET_DMA_1
E_DMA_2
E_NA_2
E_Stat_2
E_IE_2
E_LP_2
E_MII_2
ET_DMA_2
U0_DMA
U1_DMA
U2_DMA
U3_DMA
UT_DMA
U_CFG
U_IDAT
U_CTR1
U_CTR2
U_CTR3
U_STAT
U_IER
U_STAT2
U_IER2
EP0_IN_TX_INC
EP0_IN_TX_PEND
EP0_IN_TX_QWCNT
EP1_IN_TX_INC
EP1_IN_TX_PEND
EP1_IN_TX_QWCNT
EP2_IN_TX_INC
EP2_IN_TX_PEND
EP2_IN_TX_QWCNT
EP3_IN_TX_INC
EP3_IN_TX_PEND
EP3_IN_TX_QWCNT
EP_OUT_RX_DEC
EP_OUT_RX_PEND
EP_OUT_RX_QWCNT
EP_OUT_RX_BUFSIZE
EMAC 1 Source/Destination DMA Data Register
EMAC 1 Network Access Register
EMAC 1 Status Register
EMAC 1 Interrupt Enable Register
EMAC 1 Receiver Last Packet Register
EMAC 1 MII Management Interface Register
EMAC 1 Destination DMA Data Register
EMAC 2 Source/Destination DMA Data Register
EMAC 2 Network Access Register
EMAC 2 Status Register
EMAC 2 Interrupt Enable Register
EMAC 2 Receiver Last Packet Register
EMAC 2 MII Management Interface Register
EMAC 2 Destination DMA Data Register
USB Source/Destination DMA Data Register 0
USB Source/Destination DMA Data Register 1
USB Source/Destination DMA Data Register 2
USB Source/Destination DMA Data Register 3
USB Destination DMA Data Register
USB Configuration Data Register
USB Interrupt Data Register
USB Control Register 1
USB Control Register 2
USB Control Register 3
USB Status
USB Interrupt Enable Register
USB Status Register 2
USB Interrupt Enable Register 2
EP0_IN Transmit Increment Register
EP0_IN Transmit Pending Register
EP0_IN Transmit qword Count Register
EP1_IN Transmit Increment Register
EP1_IN Transmit Pending Register
EP1_IN Transmit qword Count Register
EP2_IN Transmit Increment Register
EP2_IN Transmit Pending Register
EP2_IN Transmit qword Count Register
EP3_IN Transmit Increment Register
EP3_IN Transmit Pending Register
EP3_IN Transmit qword Count Register
EP_OUT Receive Decrement Register
EP_OUT Receive Pending Register
EP_OUT Receive qword Count Register
EP_OUT Receive Buffer Size Register
0x00310000
0x00310004
0x00310008
0x0031000C
0x00310010
0x00310018
0x00310020
0x00320000
0x00320004
0x00320008
0x0032000C
0x00320010
0x00320018
0x00320020
0x00330000
0x00330008
0x00330010
0x00330018
0x00330020
0x00330024
0x00330028
0x0033002C
0x00330030
0x00330034
0x00330038
0x0033003C
0x00330040
0x00330044
0x00330048
0x0033004C
0x00330050
0x00330054
0x00330058
0x0033005C
0x00330060
0x00330064
0x00330068
0x0033006C
0x00330070
0x00330074
0x00330078
0x0033007C
0x00330080
0x00330084
RWp
RW
RW*
RW
RW*
RW3
ROp
RWp
RW
RW*
RW
RW*
RW4
ROp
RWp
RWp
RWp
RWp
RO
RW
RW
RW
RW
RW
RR
RW
RR
RW
RW
RO
(don’t care)
0x80200000
0x00000000
0x00000000
0x00000000
0x00000008
(don’t care)
(don’t care)
0x80200000
0x00000000
0x00000000
0x00000000
0x00000008
(don’t care)
(don’t care)
(don’t care)
(don’t care)
(don’t care)
(don’t care)
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
7.11.1
7.11.3
7.11.4
7.11.6
7.11.5
7.11.7
7.11.2
7.11.1
7.11.3
7.11.4
7.11.6
7.11.5
7.11.7
7.11.2
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.8.8
8.8.9
8.8.10
8.8.11
8.8.12
8.8.13
8.8.14
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
8.9.12
8.9.13
8.9.14
8.9.16
8.9.15
RO
RW
RO
RO
RW
RO
RO
RW
RO
RO
RW
RO
RO
RW
3 Note: The bit E_MII_1[1] is Read Only.
4 Note: The bit E_MII_2[1] is Read Only.
101306C
Conexant Proprietary and Confidential Information
14-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
