CX82100 Home Network Processor Data Sheet
8.9.20
USB Control-Status Register (U_CSR: 0x00330088)
Bit(s)
14
Type
RO
Default
1'b0
Name
Self clears
Receive Pending Register for All OUT Endpoints Full
EP_OUT_RX_PENDISFULL
Status.
0 = Receive Pending Register for all the OUT endpoints
is not full.
1 = Receive Pending Register for all the OUT endpoints
is full.
13
12
11
10
9
RO
RO
RO
RO
WO
1'b1
1'b1
1'b1
1'b1
1'b0
EP3_IN_TX_PENDISZERO
EP2_IN_TX_PENDISZERO
EP1_IN_TX_PENDISZERO
EP0_IN_TX_PENDISZERO
EP_OUT_RX_CLRQWCNT
Transmit Pending Register for EP3_IN Zero Status.
0 = Transmit Pending Register for EP3_IN is nonzero.
1 = Transmit Pending Register for EP3_IN is zero.
Transmit Pending Register for EP2_IN Zero Status.
0 = Transmit Pending Register for EP2_IN is nonzero.
1 = Transmit Pending Register for EP2_IN is zero.
Transmit Pending Register for EP1_IN Zero Status.
0 = Transmit Pending Register for EP1_IN is nonzero.
1 = Transmit Pending Register for EP1_IN is zero.
Transmit Pending Register for EP0_IN is Zero Status.
0 = Transmit Pending Register for EP0_IN is nonzero.
1 = Transmit Pending Register for EP0_IN is zero.
Clear Receive QWCNT Register for All OUT Endpoints.
0 = No effect.
1 = Clear the Receive QWCNT Register for all OUT
endpoints.
This bit self-clears one cycle after a 1 is written.
Clear Receive Pending Register for All OUT Endpoints.
0 = No effect.
8
WO
1’b0
EP_OUT_RX_CLRPEND
1 = Clear the Receive Pending Register for all OUT
endpoints.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit QWCNT Register for EP3_IN.
0 = No effect.
1 = Clear the Transmit QWCNT Register for EP3_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit Pending Register for EP3_IN.
0 = No effect.
1 = Clear the Transmit Pending Register for EP3_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit QWCNT Register for EP2_IN.
0 = No effect.
1 = Clear the Transmit QWCNT Register for EP2_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit Pending Register for EP2_IN.
0 = No effect.
7
6
5
4
3
WO
WO
WO
WO
WO
1’b0
1'b0
1'b0
1'b0
1'b0
EP3_IN_TX_CLRQWCNT
EP3_IN_TX_CLRPEND
EP2_IN_TX_CLRQWCNT
EP2_IN_TX_CLRPEND
EP1_IN_TX_CLRQWCNT
1 = Clear the Transmit Pending Register for EP2_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit QWCNT Register for EP1_IN.
0 = No effect.
1 = Clear the Transmit QWCNT Register for EP1_IN.
This bit self-clears one cycle after a 1 is written.
101306C
Conexant Proprietary and Confidential Information
8-35
CONEXANT [ CONEXANT SYSTEMS, INC ]
