CX82100 Home Network Processor Data Sheet
8.9.17
USB Receive DMA Watchdog Timer Register (USB_RXTIMER: 0x00330094)
Bit(s)
15:0
Type
RW
Default
16'b0
Name
USB_RXTIMER
Description
USB Receive DMA Watchdog Timer Register.
0 =
Disabled.
≠ 0 = Value copied into the USB_RXTIMERCNT bits
23:8 whenever the receive pending register value
(EP_OUT_RX_PEND) changes (increments) to a
nonzero value. See register USB_RXTIMERCNT
for more information.
8.9.18
USB Receive DMA Watchdog Timer Counter Register (USB_RXTIMERCNT:
0x00330098)
Bit(s)
23:0
Type
RO
Default
24'b0
Name
USB_RXTIMERCNT
Description
USB Receive DMA Watchdog Timer Counter Register.
This counter will start running whenever a nonzero value is
contained in USB_RXTIMER register and the receive
pending register (EP_OUT_RX_PEND) value becomes
nonzero. The counter therefore automatically reloads the
USB_RXTIMER value when it counts down to zero (this
reload condition doesn’t matter since timer has stopped) or
after a reception of a USB packet.
If bit 25 of U_IER2 is set to a 1, an interrupt will be
generated when the counter reaches zero. This is reflected
in bit 25 of U_STAT2.
“Start running” means that the 16 bits of the
USB_RXTIMER register are copied to bits 24:8 of the
counter. This allows a timer range between 256 cycles
PCLK (5.12 us if PCLK = 50MHz) and 16M cycles PCLK
(~335.5ms if PCLK = 50MHz).
The counter will stop running when the USB_RXTIMER
register is programmed to 0 or the EP_OUT_RX_PEND is
0.
8.9.19
EP_OUT Receive Pending Interrupt Level Register (EP_OUT_RX_PENDLEVEL:
0x0033009C)
Table 8-10. EP_OUT Receive Pending Level Register
Bit(s)
7:0
Type
RW
Default
8'b0
Name
Description
Receive Packet Pending Interrupt Level.
EP_OUT_RX_PENDLEVEL
When the value in the receive pending register
(EP_OUT_RX_PEND) equals the value in this register, an
interrupt will be generated if enabled.
8-34
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