CX82100 Home Network Processor Data Sheet
8.8.14
USB Interrupt Enable Register 2 (U_IER2: 0x00330044)
Writing a 1 to a bit location will enable setting of the USB Interrupt in the Interrupt
Status Register (INT_Stat) if the corresponding interrupt status bit is set in the
USB_STAT2 register. Writing a 0 will disable setting the USB Interrupt bit in the
INT_Stat register due to the corresponding interrupt status bit.
Bit(s)
31
30
29
28
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Type
RW
RW
RW
RW
RW
RW
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
Default
1’b0
1’b0
1’b0
1’b0
1'b0
1’b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
Name
Description
EP3IN_PENDTOZERO_INTEN
EP2IN_PENDTOZERO_INTEN
EP1IN_PENDTOZERO_INTEN
EP0IN_PENDTOZERO_INTEN
EP_OUT_WATCH_INTEN
EP_OUT_PENDLEVEL_INTEN
RX_OVERRUN_INTEN
CFGSET_CMD_INTEN
INTFSET_CMD_INTEN
CUR_CFG_INTEN
EP3IN_PENDTOZERO_INT Interrupt Enable.
EP2IN_PENDTOZERO_INT Interrupt Enable.
EP1IN_PENDTOZERO_INT Interrupt Enable.
EP0IN_PENDTOZERO_INT Interrupt Enable.
EP_OUT_WATCH_INT Interrupt Enable.
EP_OUT_PENDLEVEL_INT Interrupt Enable.
RX_OVERRUN_INT Interrupt Enable.
CFGSET_CMD_INT Interrupt Enable.
INTFSET_CMD_INT Interrupt Enable.
CUR_CFG_INT Interrupt Enable.
CUR_INTF_INTEN
ALTSET_CMD_INTEN
SETUP_CMD_INTEN
CUR_INTF_INT Interrupt Enable.
ALTSET_CMD_INT Interrupt Enable.
SETUP_CMD_INT Interrupt Enable.
EP3O_STALL_CLR_INT Interrupt Enable.
EP2O_STALL_CLR_INT Interrupt Enable.
EP1O_STALL_CLR_INT Interrupt Enable.
EP0O_STALL_CLR_INT Interrupt Enable.
EP3I_STALL_CLR_INT Interrupt Enable.
EP2I_STALL_CLR_INT Interrupt Enable.
EP1I_STALL_CLR_INT Interrupt Enable.
EP0I_STALL_CLR_INT Interrupt Enable.
INTR_STALL_CLR_INT Interrupt Enable.
EP3O_STALL_INT Interrupt Enable.
EP2O_STALL_INT Interrupt Enable.
EP1O_STALL_INT Interrupt Enable.
EP0O_STALL_INT Interrupt Enable.
EP3I_STALL_INT Interrupt Enable.
EP3O_STALL_CLR_INTEN
EP2O_STALL_CLR_INTEN
EP1O_STALL_CLR_INTEN
EP0O_STALL_CLR_INTEN
EP3I_STALL_CLR_INTEN
EP2I_STALL_CLR_INTEN
EP1I_STALL_CLR_INTEN
EP0I_STALL_CLR_INTEN
INTR_STALL_CLR_INTEN
EP3O_STALL_INTEN
EP2O_STALL_INTEN
EP1O_STALL_INTEN
EP0O_STALL_INTEN
EP3I_STALL_INTEN
8
7
6
5
4
3
2
1
EP2I_STALL_INTEN
EP1I_STALL_INTEN
EP0I_STALL_INTEN
INTR_STALL_INTEN
EP2I_STALL_INT Interrupt Enable.
EP1I_STALL_INT Interrupt Enable.
EP0I_STALL_INT Interrupt Enable.
0
INTR_STALL_INT Interrupt Enable.
8-28
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
