CX82100 Home Network Processor Data Sheet
Bit(s)
9
Type
RW*
Default
1’b0
Name
E_S_TF
Description
Transmit Fault.
0 = Unexpected transmit data request has not occurred during
current frame.
1 = Unexpected transmit data request has occurred during current
frame.
Transmit Jabber Timeout.
8
RW*
1’b0
E_S_TJT
0 = Jabber timer has not expired.
1 = Jabber timer has expired.
E_NA_HUJ and E_NA_HUJ must be configured for this bit to function.
No Carrier.
7
6
RW*
RW*
1’b0
1’b0
E_S_NCRS
E_S_LCRS
0 = carrier detected.
1 = No carrier (EMx_CRS pin never transitioned high) during frame
transmit.
Lost Carrier.
0 = Carrier was not lost during frame transmit.
1 = Carrier was lost (EMx_CRS pin transitioned low) at least once
frame transmit.
5
4
RW*
RW*
1’b0
1’b0
E_S_16
E_S_LC
16+ Collisions.
0 = 16 or more collisions have not occurred during frame transmit.
1 = 16 or more collisions have occurred during frame transmit.
Late Collision.
0 = A late collision (after the 64th byte) has not occurred during
frame transmit.
1 = A late collision (after the 64th byte) has occurred during frame
transmit (MIB16).
3:0
RW*
4’b0
E_S_CC
Collision Count.
Transmit collision count of the current frame. Resets after the frame is
transmitted. Increments with every collision of the current frame.
7.11.5
EMAC x Receiver Last Packet Register (E_LP_1: 0x00310010 and E_LP_2:
0x00320010)
E_LP_1 and E_LP_2 are the EMAC Receiver Last Packet registers for EMAC1 and
EMAC2, respectively. Writing to this register will clear all of its bits (as denoted by
RW*).
Bit(s)
31:10
9:6
5:2
1
Type
Default
Name
Description
Reserved.
RW*
RW*
RW*
4’b0
4’b0
1’b0
E_LP_RDMA
E_LP_RFIFO
E_LP_RI
Receive DMA State Machine State. (For test only.)
Receive FIFO State Machine State. (For test only.)
Receive Done OK from RX Buffer Manager.
0
RW*
1’b0
E_LP_TI
Transmit Done OK from TX Buffer Manager.
7-34
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